This invention relates generally to semiconductor devices, and more particularly the invention relates to high frequency (RF and microwave) power transistors and the improvement of breakdown voltage of such devices.
Power transistors and diodes are typically fabricated in a device region in a semiconductor substrate with the device region surrounded by a thick field oxide which functions as a junction termination. See FIG. 1 which illustrates in section a base region 10 of a bipolar transistor in a silicon substrate 12 and surrounded by field oxide 14. The breakdown voltage (BV) is limited by peripheral effects including curvature of the PN junction separating the base and collector due to dopant suck-up (boron for an NPN transistor base) in the field oxide and diffusion into the silicon. The oxide/silicon interface charge typically results in reduced breakdown for the NPN transistor.
FIG. 2 illustrates a modification of the structure in FIG. 1 in which a deep extrinsic base extension 11 is formed to provide a radius of curvature sufficient to maintain the required collector-base junction. Formation of the deep extrinsic base extension does require additional processing in masking, dopant implanting, and drive-in. Further, the structure still remains sensitive to oxide/silicon fixed charge and boron suck-up into the field oxide (NPN transistor). Additionally, higher device capacitance results due to increased depth and lateral dimensions of the base region.
FIG. 3 illustrates another modification which employs a lightly doped junction extension 11 around the perimeter. Again, the junction extension requires additional processing including masking, implant, and high temperature drive-in. The increased junction area results in higher device capacitance due to the increased lateral dimensions of the collector base junction.
FIG. 4 illustrates in section a fully oxide walled junction transistor which has increased breakdown voltage due to the improved electric field distribution therein. Device capacitance is minimized due to no lateral encroachment in the collector base PN junction. However, again complex processing requiring chemical-mechanical polishing, deposited conformal oxides, isotropic etching, and planarization are required.
FIG. 5 illustrates in section another prior art structure which utilizes a field plate 18 overlying the field oxide 14 and positioned around the device region in contact with the base 10. The field plate is capacitively coupled to the underlying semiconductor wafer 12 and functions as a capacitor between the base and collector of the transistor. The capacitor tends to maintain the PN junction between the base and collector by repelling electrons from the collector region (for an NPN transistor). However, the thickness of the field oxide limits the capacitance and the effect thereof in increasing breakdown voltage.
Accordingly, there is a need for a simple, low cost method and structure for increasing the junction breakdown voltage of a semiconductor device, especially for an RF and microwave power transistor, which minimizes any increase in junction capacitance.
Briefly, a method and resulting structure is provided for improving breakdown voltage without adversely affecting device capacitance by fabricating a semiconductor device in a device region in and abutting the surface of a semiconductor body such as a silicon substrate. The device region is surrounded by field oxide on the surface. In accordance with the invention, the field oxide abutting the device region is thinned such as by etching which forms a recessed area in the field oxide. Preferably, the remaining field oxide of the recessed area is approximately 0.6-1.4 xcexcm in thickness. A field plate is then formed over the recessed area which is capacitively coupled to the underlying semiconductor body. The field plate can be electrically connected to the base or emitter of a bipolar transistor or to the source or gate of a field effect transistor. For an N channel field effect transistor or an NPN bipolar transistor, this places the field plate at a lower voltage than the collector (drain) of the transistor thus repelling electrons at the collector-base drain-channel PN junction. For PNP bipolar transistors or P-channel field effect transistors, the field plate will be at a higher voltage to repel hole carriers in the substrate at the collector base junction. Alternatively, the field plate can be connected to a voltage potential (e.g., ground) or left floating or disconnected.
The process is compatible with the use of thick field oxides, and the resulting structure minimizes parasitic capacitance by permitting the use of thick field oxides while minimizing the field plate parasitic capacitance when left floating. Moreover, the processing is simple since the recess oxide etch is self-aligned to the active device region with the field plate consisting of polysilicon or metal electrodes.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawing.